A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.

A circuit includes an array of OTP cells, an array of NVM cells, an amplifier coupled to each of the array of OTP cells and the array of NVM cells, and a control circuit configured to generate one or more control signals. Responsive to the one or more control signals, the amplifier is configured to generate an output voltage based on a current received from the array of OTP cells in a first configuration, and generate the output voltage based on a voltage received from the array of NVM cells in a second configuration.

Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising an electronic memory logic element with four stable resistance states. A metamagnetic tunneling-based spin valve device for multistate magnetic memory comprising a layer of a metamagnetic material, a layer of a nonmagnetic material on the layer of a metamagnetic material, and a layer of a ferromagnetic material on the layer of a nonmagnetic material. A method of making a metamagnetic tunneling-based spin valve device for multistate magnetic memory.

The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

A magnetic domain wall movement type magnetic recording element includes: a first ferromagnetic layer which includes a ferromagnetic body; a non-magnetic layer which faces the first ferromagnetic layer; and a magnetic recording layer which faces a surface of the non-magnetic layer on a side opposite to the first ferromagnetic layer and extends in a first direction. The magnetic recording layer has a concave-convex structure on a second surface opposite to a first surface which faces the non-magnetic layer.

A magnetic domain device is provided in which a magnetic free layer (i.e., the storage layer) of a magnetic tunnel junction (MTJ) pillar is in close proximity to a conductive write line that is disposed beneath the MTJ pillar. The magnetic domain device further includes a pair of spaced apart bottom electrodes located beneath the conductive write line, and a top electrode located on the MTJ pillar. The magnetic domain device can be used in analog memories including multi-bit storage, analog memory for artificial intelligence (AI) applications.