A circuit includes an operational amplifier including an inverting input terminal capacitively coupled to each of an OTP cell array and an NVM cell array and first and second output terminals, an ADC coupled to the first and second output terminals, thereby configured to receive a differential output voltage from the operational amplifier, and a comparator coupled to the ADC and configured to output a data bit responsive to a digital output signal received from the ADC. The circuit is configured to cause the operational amplifier to generate the differential output voltage based on each of a current received from an OTP cell of the OTP cell array and a voltage received from an NVM cell of the NVM cell array.

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

A magnetoresistance effect element includes a wiring that extends in a first direction, a laminate that includes a first ferromagnetic layer connected to the wiring, a first conductive part and a second conductive part that sandwich the first ferromagnetic layer therebetween in a plan view in a lamination direction, and a resistor that has a geometrical center overlapping a geometrical center of the first conductive part or farther away from the laminate than the geometrical center of the first conductive part in the first direction when viewed in a plan view in the lamination direction.

An output, representing synaptic weights of a neural network can be received from first memory elements. The output can be compared to a known correct output. A random number can be generated with a tuned bias via second memory elements. The weights can be updated based on the random number and a difference between the output and the known correct output.

The disclosed technology relates to a multibit memory cell. In one aspect, the multibit memory cell includes a plurality of spin-orbit torque (SOT) tracks, plurality of magnetic tunnel junctions (MTJs), an electrically conductive path connecting a first MTJ and a second MTJ together, and a plurality of terminals. The plurality of terminals can be configured to provide a first SOT write current to the first MTJ, a second SOT write current to the second MTJ, and at least one of: the second SOT write current to a third MTJ, a third SOT write current to the third MTJ, and a spin transfer torque (STT) write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current through all the MTJs in series.

A two-bit memory device having a layer structure containing in order a bottom layer, a molecular layer containing a chiral compound having at least one polar functional group, and a top layer, which is electrically conductive and ferromagnetic. The chiral compound acts as a spin filter for electrons passing through the molecular layer. The chiral compound is of flexible conformation and has a conformation-flexible molecular dipole moment. An electrical resistance of the layer structure for an electrical current running from the bottom layer to the top layer has at least four distinct states which depend on the magnetization of the top layer and on the orientation of the conformation-flexible dipole moment of the chiral compound. Furthermore, a method for operating the two-bit memory device and an electronic component containing at least one two-bit memory device.

A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.