Disclosed are a 3D non-volatile memory, an operating method thereof, and a manufacturing method thereof. The 3D non-volatile memory includes a bit line formed to extend in a vertical direction and horizontal structures contacting the bit line while being formed to extend in a horizontal direction and being space in the vertical direction. Each of the horizontal structures includes a ferroelectric layer contacting the bit line, a middle metal layer surrounded by the ferroelectric layer, a dielectric layer surrounded by the middle metal layer, and a word line surrounded by the dielectric layer.

Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

A ferroelectric recording medium includes an electrode layer, a ferroelectric recording layer, and a protection layer formed in this order on a substrate, wherein the ferroelectric recording layer includes a ferroelectric layer, and a lattice constant of a material constituting the ferroelectric layer and a lattice constant of a material constituting the electrode layer or the substrate are lattice-matched within a range of ±10%.

Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

An N-bit non-volatile multi-level memory cell (MLC) can include a lower electrode and an upper electrode spaced above the lower electrode. N ferroelectric material layers can be vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2 and at least one dielectric material layer having a thickness of less than 20 nm can be located between the N ferroelectric material layers.

In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Provided is an electronic device including a first electrode; a second electrode facing the first electrode; and an active layer between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a first surface that is closest to the active layer and a second surface that is farthest from the active layer, a size of a cross-sectional horizontal area at the first surface is smaller than a size of a cross-sectional horizontal area at the second surface, the active layer includes a first region, which vertically overlaps the first surface, and a second region outside the first region, and a thickness of the active layer in the first region is smaller than a thickness of the active layer in the second region.

Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.