A memory device includes a memory cell and a controller. The memory cell includes: (a) an array of molecule chains, at least one molecule chain includes: (i) first and second binding sites positioned at first and second ends of the molecule chain, respectively, and (ii) a chain of one or more fullerene derivatives, chemically connecting between the first and second binding sites, (b) source and drain electrodes, electrically connected to the first and second binding sites, respectively, and configured to apply to the array a source-drain voltage (VSD) along a first axis, and (c) a gate electrode, configured to apply to the array a gate voltage (VG) along a second different axis. The controller is configured to perform a data storage operation in the memory cell by (i) applying to the gate electrode a signal for producing the VG, and (ii) applying the VSD between the source and drain electrodes.

An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.

Embodiments described herein include systems and techniques for converting (i.e., transducing) a quantum-level (e.g., single photon) signal between the three wave forms (i.e., optical, acoustic, and microwave). A suspended crystalline structure is used at the nanometer scale to accomplish the desired behavior of the system as described in detail herein. Transducers that use a common acoustic intermediary transform optical signals to acoustic signals and vice versa as well as microwave signals to acoustic signals and vice versa. Other embodiments described herein include systems and techniques for storing a qubit in phonon memory having an extended coherence time. A suspended crystalline structure with specific geometric design is used at the nanometer scale to accomplish the desired behavior of the system.

A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.

Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

Carbon nanotube (CNT) memory cell elements and methods of forming CNT memory cell elements are provided. A CNT memory cell may comprise a CNT memory cell element, e.g., in combination with a transistor. A CNT memory cell element may include a metal/CNT layer/metal (M/CNT/M) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a metal interconnect layer. The M/CNT/M structure may be formed by a process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped CNT layer in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped CNT layer.

A complex nanostructure, which includes a first nanostructure component having at least one aperture in a side thereof; at least one second nanostructure component having a first end and a second end, wherein the first end of each of the at least one second nanostructure is inserted through a corresponding one of the at least one aperture in the first nanostructure, thereby forming at least one junction. Embodiments of the complex nanostructure include a bifurcated nanostructure transistor constructed of linear carbon nanotubes, a multiplexer constructed of a circular carbon nanotube and multiple linear carbon nanotubes, and an information unfolder constructed of linear or a combination of linear and circular carbon nanotubes. The nanotubes may optionally be decorated with genetic material such as single-strand or double-strand human DNA segments and/or may be modified by e-beam or ozone gas to add defects into the nanotubes to alter electrical/functional characteristics.

Disclosed are a self-healing memory device including a lower electrode; a polymer nanocomposite layer formed on the lower electrode, wherein, when a structural defect occurs, the polymer nanocomposite layer repairs the structural defect and restores a memory function damaged due to the structural defect through a self-healing mechanism characterized by movement of a polymer material and hydrogen bonding; and an upper electrode formed on the polymer nanocomposite layer and a method of manufacturing the self-healing memory device.

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.