A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

A non-volatile associative memory cell includes: one magnetoresistance effect element including first and second ferromagnetic layers and a non-magnetic layer; first and second match lines connected to the magnetoresistance effect element in accordance with predetermined first and second search line voltages. The magnetoresistance effect element includes: first and second members. The first member includes first and second electrodes disposed at opposite ends. The first ferromagnetic layer is in the first or second member, the non-magnetic layer is stacked in the first direction, and the direction of internal magnetization of the first ferromagnetic layer changes in a case in which a current flows between the first and second electrodes. The non-magnetic and the second ferromagnetic layers are in the second member. A magnetoresistance effect element resistance value changes. An electric potential corresponding to an second ferromagnetic layer electric potential is applied to each of the first and second match lines.

Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability. One non-limiting example of an NV-CAM cell that employs MTJ differential sensing is a ten (10) transistor (10T)-four (4) MTJ (10T-4MTJ) NV-TCAM cell.

Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability. One non-limiting example of an NV-CAM cell that employs MTJ differential sensing is a ten (10) transistor (10T)-four (4) MTJ (10T-4MTJ) NV-TCAM cell.

A self-referenced MRAM cell comprises a first portion of a magnetic tunnel junction including a storage layer; a second portion of the magnetic tunnel junction portion including a tunnel barrier layer, a sense layer and a seed layer; the seed layer comprising a material having high spin-orbit coupling such that passing a sense current along the plane of the sense layer and/or seed layer exerts a spin-orbit torque adapted for switching a sense magnetization of the sense layer. A memory device comprising a plurality of the MRAM cells and a method for operating the memory device are also disclosed.

According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.

According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V.sub.t's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.