Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.

In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.

Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.

Embodiments of the disclosure are drawn to apparatuses and methods for content addressable memory (CAM) cells. Each CAM cell may include a comparator portion which stores a bit of information. Each CAM cell may also include a comparator portion, which compares an external bit to the stored bit. A group of CAM cells may be organized into a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change a voltage on the signal line if the external bit does not match the stored bit.

A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array. Input patterns can be loaded into a DRAM array by loading logic state ones (“1”) into each of the plurality of input data bit lines in each of the columns in the DRAM array and shunting one or more of the plurality of input data bit lines in the DRAM array corresponding to logic state zeroes (“0”) in the input pattern.

The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

A semiconductor device that enables a memory size reduction is provided. The semiconductor device includes a converter circuit, a memory circuit, and a detection circuit. The converter circuit has a function of converting first data that includes a digital voltage value to second data that includes an analog current value. The memory circuit has a function of storing third data that includes an analog current value. The detection circuit has a function of generating data that indicates whether the analog current values of the second and third data match.

A system includes a read/write module and a caching module. The read/write module is configured to access a first portion of a recording surface of a rotating storage device. Data is stored on the first portion of the recording surface of the rotating storage device at a first density. The caching module is configured to cache data on a second portion of the recording surface of the rotating storage device at a second density. The second portion of the recording surface of the rotating storage device is separate from the first portion of the recording surface of the rotating storage device. The second density is less than the first density.