A memory device is provided to include: a plurality of memory cells; a peripheral circuit configured to perform an operation on the plurality of memory cells; a temperature circuit configured to measure a temperature of the memory device; a monitoring component configured to generate, based on whether a measured temperature is within a reference range, monitoring information representing an operation mode that is either a normal mode in which the operation is performed or a protection mode in which the operation is suspended; and an operation controller configured to output a signal for controlling the operation according to the monitoring information. The monitoring component is further configured to store the monitoring information and output the monitoring information to the operation controller in response to receiving the measured temperature from the temperature circuit.

Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

A memory device for data searching and a data searching method thereof are provided. The data searching method includes the following steps. A searching word is received and then divided into a plurality of sections. The sections are encoded as a plurality of encoded sections, so that the encoded sections may correspond to a plurality of memory blocks in a memory array. The encoded sections are directed into the memory blocks to perform data comparisons and obtaining a respective result of data comparison. Thereafter, addresses of bit lines which match the searching word are obtained according to respective result of data comparison for each of memory block.

Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

Disclosed is a TCAM device based on a ternary memory cell. A TCAM cell includes a ternary memory cell for storing ternary data and a comparison circuit for obtaining a stored value stored in the ternary memory cell and a search value input via a search line of a search driver, identifying a data match between the stored value and the search value, and outputting a result of the identification via a match line. The comparison circuit includes a first transistor pair that receives an inverted stored value that is an inverted value of the stored value of the ternary memory cell and the search value and a second transistor pair that receives the stored value of the ternary memory cell and an inverted search value that is an inverted value of the search value. The first transistor pair and the second transistor pair are connected in parallel to each other.

Techniques for implementing a fault-tolerant power supply are described. In an example, a system converts an alternating-current (AC) voltage to an initial direct current (DC) voltage. The system further converts the initial DC voltage to a first DC voltage and a second DC voltage. The system applies the first DC voltage to a high-priority device such as a metrology device. The system applies the second DC voltage to a low-priority or peripheral device. When the initial DC voltage is outside a voltage range, the system deactivates the second DC voltage to the lower-priority device and maintains the first DC voltage to the metrology device.

The present invention is directed to binding molecules that possess one or more epitope-binding sites specific for an epitope of CD137 and one or more epitope-binding sites specific for an epitope of a tumor antigen (“TA”) (e.g., a “CD137×TA Binding Molecule”). In one embodiment, such CD137×TA Binding Molecules will be bispecific molecules, especially bispecific tetravalent diabodies, that are composed of two, three, four or more than four polypeptide chains and possessing two epitope-binding sites each specific for an epitope of CD137 and two epitope-binding sites each specific for an epitope of a TA. Alternatively, such CD137×TA Binding Molecules will be bispecific molecules, especially bispecific trivalent binding molecules composed of three or more polypeptide chains and possessing one or two epitope-binding sites each specific for an epitope of CD137 and one or two epitope-binding sites each specific for an epitope of a TA. The CD137×TA Binding Molecules of the invention are capable of simultaneous binding to CD137, and a TA. The invention is directed to pharmaceutical compositions that contain any such CD137×TA Binding Molecules. The invention is additionally directed to methods for the use of such molecules in the treatment of cancer and other diseases and conditions. The invention also provides novel CD137-binding molecules, and HER2/neu-binding molecules, as well as derivatives thereof and uses thereof.

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.