An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source.

A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least one light-absorbing film above the floating gate, wherein at least one light-absorbing film is provided with dummy via holes overlapping the floating gate, and a dielectric layer on the light-absorbing film and filling up the dummy via holes.

An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source.

Programmable devices and methods for fabricating the programmable devices are described. In an example, a method for fabricating a programmable device can include bonding a UV light source to a computer chip by flip-chip mounting the UV light source to the computer chip. The UV light source can be configured to emit UV light towards a UV erasable area of the computer chip to perform UV erasing on the computer chip. The method can further include bonding a carrier to the computer chip by flip chip mounting the computer chip to the carrier using a second array of bond pads.

Programmable devices and methods for fabricating the programmable devices are described. In an example, a method for fabricating a programmable device can include bonding a UV light source to a computer chip by flip-chip mounting the UV light source to the computer chip. The UV light source can be configured to emit UV light towards a UV erasable area of the computer chip to perform UV erasing on the computer chip. The method can further include bonding a carrier to the computer chip by flip chip mounting the computer chip to the carrier using a second array of bond pads.

Provided is an optically restorable semiconductor device including a gate electrode, a gate insulation film on the gate electrode, a photo-responsive semiconductor film on the gate insulation film, and an interface charge part disposed adjacent to an interface between the photo-responsive semiconductor film and the gate insulation film, wherein the interface charge part includes charge traps, and the interface charge part and the photo-responsive semiconductor film directly contact with each other.

Provided is an optically restorable semiconductor device including a gate electrode, a gate insulation film on the gate electrode, a photo-responsive semiconductor film on the gate insulation film, and an interface charge part disposed adjacent to an interface between the photo-responsive semiconductor film and the gate insulation film, wherein the interface charge part includes charge traps, and the interface charge part and the photo-responsive semiconductor film directly contact with each other.

A nonvolatile memory device includes: a plurality of word lines that are stacked; a pillar structure that penetrates through the word lines in a vertical direction; and a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure. The pillar structure includes: a vertical channel region disposed in a core; and a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.