A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify operations. The programming operations include applying a programming voltage to the selected word line, and the verify operations include applying a verify voltage to the selected word line. At least one programming loop of the plurality of programming loops further includes a pre-verify operation. The pre-verify operation includes applying a pre-read voltage to the selected word line. The pre-read voltage is less than the verify voltage.

The present technology relates to an electronic device. According to the present technology, a memory device having improved verify accuracy may include a memory block including memory cells, a read and write circuit including a plurality of page buffers, a current sensing circuit configured to perform a verify operation of comparing sensing voltages with a reference voltage, and a control logic configured to control the current sensing circuit to perform the verify operation. The control logic controls performing a first verify operation on each of page buffer groups having a same logical group number, and performing a second verify operation on each of page buffer groups having a same physical group number, and the current sensing circuit outputs a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.

There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.

A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.

A storage device that includes a non-volatile memory with a control circuitry is provided. The control circuitry is communicatively coupled to a memory block that includes an array of memory cells. The control circuitry is configured to program one or more bits of data into the memory cells. The control circuitry is further configured to operate the non-volatile memory in a multi-bit per memory cell mode, monitor a usage metric while the non-volatile memory is operating in the multi-bit per memory cell mode, and determine if the usage metric has crossed a predetermined threshold. In response to the usage metric not crossing the predetermined threshold, the control circuitry continues to operate the non-volatile memory in the multi-bit per memory cell mode. In response to the usage metric crossing the predetermined threshold, the control circuitry automatically operates the non-volatile memory in a single-bit per memory cell mode.

A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.