In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation: $V_{\mathrm{MAX}}=\left(1+\frac{.Math.Z_2.Math.}{.Math.Z_1.Math.}\right)t_F{E}_{\mathrm{FM}}$ where V.sub.MAX is a capacitance boosting operating voltage, Z.sub.1 is impedance of the ferroelectric film, Z.sub.2 is impedance of the dielectric film, t.sub.F is a thickness of the ferroelectric film, and E.sub.FM is an electric field applied to the ferroelectric film having a maximum polarization.

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation:

[00001]$V_{\mathrm{MAX}}=\left(1+\frac{.Math.Z_2.Math.}{.Math.Z_1.Math.}\right)t_F{E}_{\mathrm{FM}}$

where V.sub.MAX is a capacitance boosting operating voltage, Z.sub.1 is impedance of the ferroelectric film, Z.sub.2 is impedance of the dielectric film, t.sub.F is a thickness of the ferroelectric film, and E.sub.FM is an electric field applied to the ferroelectric film having a maximum polarization.

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation:

[00001]$V_{\mathrm{MAX}}=\left(1+\frac{.Math.Z_2.Math.}{.Math.Z_1.Math.}\right)t_F{E}_{\mathrm{FM}}$

where V.sub.MAX is a capacitance boosting operating voltage, Z.sub.1 is impedance of the ferroelectric film, Z.sub.2 is impedance of the dielectric film, t.sub.F is a thickness of the ferroelectric film, and E.sub.FM is an electric field applied to the ferroelectric film having a maximum polarization.

A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation: $V_{\mathrm{MAX}}=\left(1+\frac{.Math.Z_2.Math.}{.Math.Z_1.Math.}\right)t_F{E}_{\mathrm{FM}}$
where V.sub.MAX is a capacitance boosting operating voltage, Z.sub.1 is impedance of the ferroelectric film, Z.sub.2 is impedance of the dielectric film, t.sub.F is a thickness of the ferroelectric film, and E.sub.FM is an electric field applied to the ferroelectric film having a maximum polarization.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift register includes a plurality of rotors arranged along one direction and provided with a uniaxial anisotropy. Each of the plurality of rotors has a characteristic direction rotatable around a rotational axis extending in the one direction. The program/read element is configured to program data to the shift register by causing the characteristic direction of one of the rotors to match one selected from two directions conforming to the uniaxial anisotropy and configured to read the data by detecting the characteristic direction. The rotating force application unit is configured to apply a rotating force to the shift register to urge the characteristic direction to rotate. The plurality of rotors are organized into a plurality of pairs of every two mutually adjacent rotors. A first force acts to urge the characteristic directions to be opposingly parallel for two of the rotors belonging to the same pair. A second force acts to urge the characteristic directions to be opposingly parallel for two mutually adjacent rotors belonging to mutually adjacent pairs.

A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.