A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

A shift register, comprising an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to transmit a first voltage signal from a first voltage signal terminal to a first node under the control of an input signal from a signal input terminal. The first control circuit is configured to transmit a second voltage signal from a second voltage signal terminal to a second node under the control of a first clock signal from a first clock signal terminal and the voltage of the first node. The second control circuit is configured to transmit a second clock signal from a second clock signal terminal to a third node under the control of the voltage of the second node. The output circuit is configured to transmit the first voltage signal from the first voltage signal terminal to a scan signal output terminal under the control of the voltage of the third node.

A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

The present invention is directed towards a tubular nanosized magnetic wire, wherein the nanosized magnetic wire comprises: a tubular magnetic shell surrounding a longitudinal axis of the wire, at least one region of the tubular magnetic shell is capable of providing a 360 magnetic domain wall, wherein the 360 magnetic domain wall is self-stabilizing and has a magnetization going from a parallel alignment to a perpendicular alignment and to a parallel alignment with regards to the wire axis. The present invention also provides a practical method capable of making a tubular nanosized magnetic wire with a self-stabilizing, 360 magnetic domain wall. The present invention also relates to the use of the tubular nanosized magnetic wire in a racetrack memory device.

A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of the hexagonal cylindrical pores, that is in a range in a range of about 100 mm.sup.2 to about 900 mm.sup.2.

A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of the hexagonal cylindrical pores, that is in a range in a range of about 100 mm.sup.2 to about 900 mm.sup.2.

A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of the hexagonal cylindrical pores, that is in a range in a range of about 100 mm.sup.2 to about 900 mm.sup.2.

Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.