G11C19/38

Two dimensional masked shift instruction
11544060 · 2023-01-03 · ·

An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.

Two dimensional masked shift instruction
11544060 · 2023-01-03 · ·

An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.

IMAGE SENSING SYSTEM AND IMAGE SENSING DATA PROCESSING METHOD
20230156359 · 2023-05-18 · ·

An image sensing system comprising: a storage device, comprising at least two first registers, wherein a number of the first registers following a first direction of the storage device is larger than a number of the first registers following a second direction of the storage device; a filter, comprising at least two second registers; and an SIPO (serial in parallel out) circuit, coupled between the storage device and the filter.

OPERATION OF AN ULTRASONIC SENSOR

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

OPERATION OF AN ULTRASONIC SENSOR

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

Address circuit
09805819 · 2017-10-31 · ·

Described herein are techniques, systems, and circuits for addressing image data according to blocks. For example, in some cases, the address space may be divided into high order address bits and low order address bits. In these cases, an address circuit may twist an address space by shifting the high order bits and low order bits of an address in a rightward direction, shifting the low order bits of the address in a leftward direction, and shifting the high order bits and the low order bits of the address in the leftward direction. The circuit may modify the address value and untwist the address space. For example, the untwisting may include shifting the high order bits and the low order bits of an address in the rightward direction, shifting the low order bits of the address in the rightward direction, and shifting the high order bits and the low order bits of the address in the leftward direction.

Address circuit
09805819 · 2017-10-31 · ·

Described herein are techniques, systems, and circuits for addressing image data according to blocks. For example, in some cases, the address space may be divided into high order address bits and low order address bits. In these cases, an address circuit may twist an address space by shifting the high order bits and low order bits of an address in a rightward direction, shifting the low order bits of the address in a leftward direction, and shifting the high order bits and the low order bits of the address in the leftward direction. The circuit may modify the address value and untwist the address space. For example, the untwisting may include shifting the high order bits and the low order bits of an address in the rightward direction, shifting the low order bits of the address in the rightward direction, and shifting the high order bits and the low order bits of the address in the leftward direction.

OPERATION OF AN ULTRASONIC SENSOR

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

OPERATION OF AN ULTRASONIC SENSOR

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

One direction-shift register aliasing table circuit suitable for use in microprocessors
11817162 · 2023-11-14 ·

Disclosed are hardware configurations of the Register Aliasing Table (RAT) which are suitable for use in structures such as modern microprocessor, microcontroller, CPU etc. that use pipe line technique, perform multi-command operations, prevents Write After Read (WAR), Write After Write (WAW), Read After Write (RAW) dependencies. The Register Aliasing Table provides a circuit which consumes less energy, uses less space and has low latency compared to the applications in the state of the art.