A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.

A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.

A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.

A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.