Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.

Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures.

A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

In a coarse programming, the threshold voltage of the memory cell is programmed to a first level representative of N−1 bit values data according to a first mapping between combinations of values of N−1 possible bits and threshold levels. A group identification is representative of whether the first level is an odd or even numbered level in the first mapping. For a fine programming, the memory cell is read, based on the group identification, to obtain the N−1 bit values; and at least one additional bit is received to join the N−1 bit values to form at least N bit values. The threshold voltage of the memory cell is then finely programmed to a second level representative of the at least N bit values according to a second mapping between combinations of values of the at least N possible bits and threshold levels.

A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.

Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.

In a coarse programming, the threshold voltage of the memory cell is programmed to a first level representative of N−1 bit values data according to a first mapping between combinations of values of N−1 possible bits and threshold levels. A group identification is representative of whether the first level is an odd or even numbered level in the first mapping. For a fine programming, the memory cell is read, based on the group identification, to obtain the N−1 bit values; and at least one additional bit is received to join the N−1 bit values to form at least N bit values. The threshold voltage of the memory cell is then finely programmed to a second level representative of the at least N bit values according to a second mapping between combinations of values of the at least N possible bits and threshold levels.

Embodiments adaptively determine a read retry threshold voltage for a next read operation using meta information collected from previous failed read data. A controller obtains meta information associated with a read operation on a select page, the meta information including a read threshold voltage set. The controller determines a mathematical model for estimating a checksum value for data associated with a next read operation, using a set function of the read threshold voltage set and a set checksum value. The controller determines a set of parameters by performing polynomial regression on the mathematical model. The controller estimates a next read threshold voltage for the next read operation based on the set of parameters.

A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.