Provided herein may be a memory system. The memory system may include a memory device including a memory block and a peripheral circuit, and a memory controller configured to transmit a program command based on a single-level cell scheme to the memory device so as to increase threshold voltages of the selection transistors included in the memory block after an erase operation has been performed on the memory block, and transmit, to the memory device, a read command to perform a check operation, wherein the read command indicates a first read voltage and a second read voltage higher than the first read voltage, and the check operation includes a check of whether the threshold voltages fall within a range between the first and second read voltages, or a check of whether the threshold voltages are lower than the first read voltage or higher than the second read voltage.

A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a data structure mapping block identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block of the memory device, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block, and reading, using the determined set of read levels, data from the block of the memory device.

Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein the sequence comprises a sequence of digital data, write the sequence associated with a user data to the memory device, read out a read data including the sequence and the associated user data, analyze the sequence to understand characters of the read data and create analysis result by the sequence analyzer, identify an optimal threshold voltage in accordance with the analysis result, and provide the optimal threshold voltage to an ECC engine.

A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.

Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.