A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

A memory device includes at least one bit line, at least one word line, and at least one memory cell. The memory cell includes a first transistor, a plurality of data storage elements, and a plurality of second transistors corresponding to the plurality of data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each data storage element among the plurality of data storage elements and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line.

Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Various embodiments provide methods for configuring a phase-change random-access memory (PCRAM) structures, such as PCRAM operating in a single-level-cell (SLC) mode or a multi-level-cell (MLC) mode. Various embodiments may support a PCRAM structure being operating in a SLC mode for lower power and a MLC mode for lower variability. Various embodiments may support a PCRAM structure being operating in a SLC mode or a MLC mode based at least in part on an error tolerance for a neural network layer.

Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

A resistive random access memory array and an operation method therefor, and a resistive random access memory circuit. The resistive random access memory array includes multiple memory cells, multiple bit lines, multiple word lines, multiple block selection circuits, and multiple initialization circuits. Each memory cell includes a resistive random access memory device and a switching device. The multiple memory cells are arranged into multiple memory cell rows and multiple memory cell columns in a first direction and a second direction, and the multiple bit lines and the multiple memory cell columns are connected in one-to-one correspondence. Each block selection circuit is configured to write a read/write operation voltage into a correspondingly connected bit line in response to a block selection voltage. Each initialization circuit is configured to write an initialization operation voltage to a correspondingly connected bit line in response to an initialization control voltage.

A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

A phase change (PCM) memory device that includes a PCM and a resistance-capacitance (RC) circuit. The PCM has one or more PCM properties, each PCM property has a plurality of PCM property states. As the PCM property states of a given property are Set or Reset, the PCM property states each produce an incremental change to a property level of the respective/associated PCM property, e.g., PCM conductance. The incremental changes to property level of the PCM memory device are in response to application of one or more of a pulse number of voltage pulses. The RC circuit produces a configuring current that flows through the PCM in response to one or more of the voltage pulses. The configuring current modifies one or more of the incremental changes to one or more of the property levels so that the property level changes lineally with respect to the pulse number. The PCM memory device has use in a synapse connector, e.g., in a memory array. The memory array can be used to store and/or read memory values associated with one or more of the property levels. The memory values can be used as weighting values in a neuromorphic computing application/system, like a neural network.

In an embodiment, a method includes receiving, between a positive input terminal and a negative input terminal, a supply voltage, receiving a data signal, generating, by a voltage generator in a branch of a plurality of branches, a branch current as a function of a respective driving signal and of a regulated voltage, each branch connected between the positive input terminal and the negative input terminal, selectively activating the voltage generator as a function of a respective enabling signal and providing, between a positive output terminal and a negative output terminal, the regulated voltage to one or more driving circuits.