A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

A control apparatus controls an array-type sensor. The control apparatus includes: a first selector/driver that is configured to select and drive one of a plurality of first lines; a second selector/driver that is configured to select and drive at least one of a plurality of second lines; a read/arithmetic circuit that is configured to read outputs of respective unit cells and perform a correction operation on the outputs; and a nonvolatile storage device that is configured to store reference data. The sensor outputs of the respective unit cells with respect to two or more reference inputs are stored as reference data in the nonvolatile storage device in a calibration mode, and a correction operation is performed on the sensor outputs of the respective unit cells using the stored reference data and results of the correction operation are output in a measurement mode.

A control apparatus controls an array-type sensor. The control apparatus includes: a first selector/driver that is configured to select and drive one of a plurality of first lines; a second selector/driver that is configured to select and drive at least one of a plurality of second lines; a read/arithmetic circuit that is configured to read outputs of respective unit cells and perform a correction operation on the outputs; and a nonvolatile storage device that is configured to store reference data. The sensor outputs of the respective unit cells with respect to two or more reference inputs are stored as reference data in the nonvolatile storage device in a calibration mode, and a correction operation is performed on the sensor outputs of the respective unit cells using the stored reference data and results of the correction operation are output in a measurement mode.

Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.

Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

Provided are a method for fabricating nano structures which includes: preparing a substrate; preparing a polymer including a plurality of metal atoms; applying the polymer to the substrate to attach the metal atoms onto the substrate; and making one or more metallic nano particles from the metal atoms.

An electronic component (1) and an electronic device (100) comprising one or more such components (1). The electronic component (1) comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one insulating or semi-insulating layer (7) between said electrodes. The stack further comprises a buffer layer (13), arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.