An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.

A memory cell array includes a plurality of memory blocks, each memory block having a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder circuit is connected to the plurality of memory cells through a plurality of word lines, selecting a first memory block of the plurality of memory blocks. A page buffer circuit is connected to the plurality of memory cells through a plurality of bit lines. A control logic circuit applies an erase voltage to the substrate during an erase operation, outputting a word line voltage having a first word line voltage and a second word line voltage to the row decoder circuit. During the erase operation, the row decoder circuit applies the first word line voltage to each word line of the first memory block and then applies the second word line voltage to each word line.

A mobile electronic device including an interface unit, a semiconductor storage device and a processor is provided. The interface unit provides a user interface to receive a user input. The semiconductor storage device includes a controller and a non-volatile memory. The non-volatile memory is coupled to the controller and includes a plurality of memory blocks. The processor is coupled to the interface unit and the semiconductor storage device. The processor sends a signal to the semiconductor storage device in response to the user input. The controller clears at least one of the memory blocks in response to the signal.

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.

The invention provides a storage structure and an erase method thereof, capable of performing an erase operation on a plurality of memory blocks. The storage structure includes: a first storage body, a second storage body, a third storage body, and a controller. Memory blocks that are consecutively numbered are sequentially alternately stored in the first memory bank, the second memory bank, and the third memory bank, and the controller is configured to control each memory block to sequentially undergo a first process, a second process and a third process. The erase method includes: when a memory block Bi undergoes the third process, a memory block Bi+1 undergoes the second process, and a memory block Bi+2 undergoes the first process at the same time; where i ∈ [1, n−2]. Three adjacent blocks undergo the first process, the second process, and the third process simultaneously.

Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.