There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells; and a peripheral circuit for performing a program operation and an erase operation on the memory block. The program operation is performed by using a hole injection method, and the erase operation is performed by using an electron charging method. The plurality of memory cells are programmed when a threshold voltage of each of at least some of the plurality of memory cells is decreased to be less than a set level in the program operation, and are erased when the threshold voltage of each of the plurality of memory cells is increased to be the set level or higher in the erase operation.

There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells; and a peripheral circuit for performing a program operation and an erase operation on the memory block. The program operation is performed by using a hole injection method, and the erase operation is performed by using an electron charging method. The plurality of memory cells are programmed when a threshold voltage of each of at least some of the plurality of memory cells is decreased to be less than a set level in the program operation, and are erased when the threshold voltage of each of the plurality of memory cells is increased to be the set level or higher in the erase operation.

A non-volatile reverse memory cell suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.

A non-volatile reverse memory cell suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

Methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. The apparatus may be configured to determine a polarity data associated with reading data stored at a target location. In reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.

Examples of the present disclosure provide a memory and an operation method thereof, a memory system and an electronic device. The operation method comprises: applying a pass voltage to word lines coupled to unselected memory cells of one of memory strings according to a program order of a selected memory cell of the memory string when performing a read operation on the selected memory cell, wherein the earlier the program order of the selected memory cell is, the greater the pass voltage applied to the word lines coupled to the unselected memory cells of the memory string during the read operation is. In the examples of the present disclosure, the pass voltage applied to the word lines coupled to the unselected memory cells is determined according to the program order of the selected memory cell, i.e., according to different degrees of impact of a background pattern dependency effect experienced by the selected memory cell, such that the impact of the background pattern dependency effect can be decreased, and the read disturb is reduced.

A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation. A pre-charge operation occurs in which a channel voltage is increased to a positive level. This reduces a channel gradient which can lead to a disturb of the select gate transistors. One approach involves applying a voltage at an intermediate level to the source and/or drain ends of the memory strings, before increasing the voltage from the intermediate level to a peak erase level. Another approach involves driving the word line voltages at a negative level and then at a higher level to down couple and then up couple the channel voltages. The techniques may be adjusted depending on whether the word lines are at a positive floating voltage at a start of the erase operation, and based on a level of the floating voltage.

A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.

A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.