Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.

The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.

An anti-fuse device includes: a substrate; an anti-fuse gate, partially embedded in the substrate, a portion of the anti-fuse gate embedded in the substrate having one or more sharp corners; and an anti-fuse gate oxide layer, located between the anti-fuse gate and the substrate.

A system-on-chip (SoC) includes a fuse circuit and decoding circuitry. The fuse circuit includes functional fuses, control fuses utilized as the functional fuses, and fuses configured to store override data that indicates an association between the functional fuses and the control fuses utilized as the functional fuses. The decoding circuitry is configured to output configuration data associated with a configuration of the fuse circuit based on the override data and an initial configuration of the fuse circuit. In such a scenario, functional operations of the SoC are executed based on the configuration data. Alternatively, the decoding circuitry is configured to output a set of functional data based on the override data and various functional data stored in the functional fuses and the control fuses utilized as the functional fuses. In such a scenario, the functional operations are executed based on the outputted set of functional data.

An apparatus includes a boot-up control circuit configured to, when a first boot-up operation is performed, latch first fuse data by receiving the first fuse data and fuse information from a fuse circuit and configured to, when a second boot-up operation is performed, latch second fuse data by receiving the second fuse data from the fuse circuit based on the fuse information; and a rupture control circuit configured to store a failure address as the second fuse data by rupturing the fuse circuit based on the fuse information.

Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.

An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.

Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.

Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.