A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

An organic light-emitting display panel, driving method thereof, and an organic light-emitting display device are provided. The organic light-emitting display panel comprises a plurality of pixel driving circuits including a first, a second and a third pixel driving circuits along a row direction. The first and the second pixel driving circuits share a same reference voltage signal line. The second and the third pixel driving circuits share a same data voltage signal line. A plurality of reference voltage signal lines is connected to the plurality of pixel driving circuits. A plurality of data voltage signal lines is connected to the plurality of pixel driving circuits. A first control signal line is connected to the first and third pixel driving circuits. A second control signal line is connected to the second pixel driving circuit. A light-emitting control signal line is connected to the first, second, and third pixel driving circuits.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit 1 including a differential amplifier circuit 10, a switch circuit 20, and a hold capacitor C.sub.21, the differential amplifier circuit 10 includes a first resistor R.sub.11 having one end connected to a collector electrode of a first transistor Q.sub.11 constituting a differential pair, a second resistor R.sub.12 having one end connected to the collector electrode of a second transistor Q.sub.12 constituting the differential pair, and a third resistor R.sub.13 to which the other end of the first resistor R.sub.11 and the other end of the second resistor R.sub.12 are connected and which is connected between the other ends and a power supply V.sub.CC.

The transistor comprises a first insulation layer and at least one switch region; a first function layer and a second function layer are respectively disposed on each side of the first insulation layer in the x direction; a first source is disposed in a source region of the first semiconductor layer, and a first drain is disposed at a drain region of the first semiconductor layer; a second source is disposed in a source region of the second semiconductor layer, and is connected to the first source by a first connection line; a second drain is disposed in a source region of the second semiconductor layer, and is connected to the first drain by a second connection line; the gate structure is insulated from the first semiconductor layer and the second semiconductor layer and is disposed opposite to channel regions of the first semiconductor layer and the second semiconductor layer.

The transistor comprises a first insulation layer and at least one switch region; a first function layer and a second function layer are respectively disposed on each side of the first insulation layer in the x direction; a first source is disposed in a source region of the first semiconductor layer, and a first drain is disposed at a drain region of the first semiconductor layer; a second source is disposed in a source region of the second semiconductor layer, and is connected to the first source by a first connection line; a second drain is disposed in a source region of the second semiconductor layer, and is connected to the first drain by a second connection line; the gate structure is insulated from the first semiconductor layer and the second semiconductor layer and is disposed opposite to channel regions of the first semiconductor layer and the second semiconductor layer.

A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement device induces charge movement to or from one of the pair of reservoirs, the rate of charge movement programmed to one of add or remove charges at a rate proportional to the first charge movement device. The first charge movement device loads a first charge into a first of the pair of charge reservoirs during a first cycle. The first charge movement device and the second charge movement device remove charges at a proportional rate from the pair of charge reservoirs during a second cycle until the first of the pair of charge reservoirs is depleted of the first charge. The second charge reservoir thereafter holding the multiplied result.