A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.

A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

A method and a testing apparatus related to wafer testing are provided. In the method, testing raw data is obtained by a testing apparatus operating with a Unix-related system. The testing raw data is a testing result of probe testing on one or more wafers by the testing apparatus. The testing raw data is converted into converted data by the testing apparatus. The converted data is related to the defect information of the wafer. Analyzed data is generated by the testing apparatus according to the converted data. The analyzed data is used for a graphical interface. Therefore, real-time defect analysis during the testing procedure may be provided.

A memory device includes a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result, a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit, and an output data alignment circuit suitable for converting the read path data into serial data to output the serial data as output data.

A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.

A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.