Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform a verify operation of comparing threshold voltages of the memory cells with a verify voltage on each of a plurality of program levels. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and determine a start time point of a verify operation corresponding to a next program level of the target level using the number of fail bits for each of the plurality of blind voltages.

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.

A memory performs a sequence of ECS operations to read a codeword, detect and correct any errors, and write the corrected codeword back to the memory array. An ECS circuit counts errors which are detected, and sets a value of one or more ECS registers in a mode register if the count exceeds a threshold filter at the end of the ECS cycle. The memory also includes a forced ECS readout circuit, which responsive to a command, for example from a controller, sets the value(s) in the ECS register(s).

A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.