A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

A method includes receiving, by a memory sub-system, host data to be written to a plurality of blocks of a memory device associated with a memory sub-system, where each of the plurality of blocks are coupled to one of a plurality of word lines of the memory device. The method can further include generating parity data for each word line of the block; dividing the parity data into one of either a first word line parity set or a second word line parity set; generating a reduced parity data set with exclusive or parity values for the first word line parity set and for the second word line parity set; and writing the reduced parity data set in the memory sub-system.

Methods, systems, and computer-readable media (transitory or non-transitory) are described herein for automatic backup and replacement of a storage device. According to an example, a storage failure for given storage device may be predicted. A backup process of the give storage device to a remote system may be initiated based on predicting the storage failure for the given storage device. The backup process may create a one-to-one image backup or a user data backup based on a predicted amount of time until the storage failure of the given storage device. A restore process of a new storage device at the remote system may be initiated upon completion of the backup process. The restore process may depend on the backup created during the backup process and/or various types of new storage devices that are available. The new storage device may be based on the given storage device.

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks, each block having a plurality of pages, each page having a plurality of memory cells, wherein the plurality of memory block includes an SLC (Single Level Cell) block and an MLC (Multi-Level Cell) block; and a controller suitable for programming input data transmitted from a host to both the SLC block and the MLC block in response to a first program command, and invalidating the input data programmed in the SLC block at a time point when the program operation for the MLC block is completed, when the memory system is powered on after an SPO (Sudden Power-Off) occurred while the program operation was performed on both the SLC block and the MLC block, the controller may perform a recovery operation to the MLC block based on valid data programmed in the SLC block.

A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.