Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.

A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.

A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

A method of operating a memory device includes; receiving a refresh command, performing a refresh operation on a target row of a bank memory array, and providing status information to a memory controller for an adjacent row, relative to the target row, during a refresh operation period defining a refresh operation performed by the memory device.

A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.

A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

A memory core including a memory core including memory cells that are arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit suitable for storing an address and a risk score of each of activated rows among the rows, wherein the refresh target selection circuit is further suitable for increasing the risk score of a corresponding row whenever the corresponding row is activated, whenever a row at a ‘+2’ position of the corresponding row is activated, and whenever a row at a ‘−2’ position of the corresponding row is activated.

A semiconductor memory device includes: a plurality of banks having a data storage unit and an error correction code storage unit; an error correction code generation unit; an error correction unit; a low counter that determines a low address as a refresh target; a bank counter that determines a bank address as an error correction target; and a column counter that determines a column address as the error correction target. The error correction unit performs the error correction process on a data of an error correction target address determined based on the low counter, the bank counter, and the column counter when receiving a refresh command.