Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

A semiconductor device includes a memory bank including a first memory block, a second memory block, and a redundancy memory block, and a column line selection circuit configured, when a fail occurs in a first column line of the first memory block, to replace the first column line of the first memory block with a first redundancy line of the redundancy memory block, and replace a second column line of the second memory block with a second redundancy line of the redundancy memory block.

A memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array are independent. The first memory array includes a plurality of general bits and the second memory array includes a plurality of spare bits. An address of defective bit in the first memory array is stored in the second memory array, and the memory circuit repairs the defective bit by one of the spare bits according to the address.

A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.