Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.

Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

Embodiments of the present disclosure provide a method and an apparatus of testing a word line. After repair of a memory array is completed, if a target word line in a failure state exists in the memory array, a second numerical value is written into the target word line, and then it is determined, according to a numerical value outputted by each word line in the memory array, whether there are at least two word lines in an on-state in the memory array; if there are at least two word lines in an on-state simultaneously in the memory array, a current value generated by the target word line in an on-to-off process is detected; when the current value generated by the target word line in the on-to-off process is greater than a preset current threshold, it is determined that the target word line has a repair fault.

A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

A method of managing errors in a plurality of storage drives includes receiving, at a memory controller coupled to at least one storage medium in an SSD, a read command from a host interface. The method also includes retrieving, from the storage medium, read data corresponding to a plurality of data chunks to be retrieved in response to the read command, and determining that at least one data chunk of the plurality of data chunks is unable to be read, the at least one data chunk corresponding to a failed data chunk. And in response to determining the failed data chunk, sending to the host interface the read data including the failed data chunk or excluding the failed data chunk. And in response to the read command sending to the host interface status information about all data chunks.

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.