Low spike count ring buffer mechanisms on neuromorphic hardware are provided. A ring buffer comprises a plurality of memory cells. The plurality of memory cells comprises one or more neurosynaptic core. A demultiplexer is operatively coupled to the ring buffer. The demultiplexer is adapted to receive input comprising a plurality of spikes, and write sequentially to each of the plurality of memory cells. A plurality of output connectors is operatively coupled to the ring buffer. Each of the plurality of output connectors is adapted to provide an output based on contents of a subset of the plurality of memory cells.

Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.

A semiconductor storage device includes a memory cell array, and a peripheral circuit that is connected to the memory cell array, and that inputs and outputs user data in response to an input of a command set including command data and address data. The peripheral circuit includes a command register, an address register, and a queue register. The command register includes an n-bit first register column capable of storing n-bit data forming the command data. The address register includes an n-bit second register column capable of storing n-bit data forming the address data. The queue register includes a plurality of third register columns, each capable of storing at least (n+1) bit data, and each third register column is capable of storing the n-bit data forming the command data or the n-bit data forming the address data.

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

A semiconductor storage device includes a memory cell array, and a peripheral circuit that is connected to the memory cell array, and that inputs and outputs user data in response to an input of a command set including command data and address data. The peripheral circuit includes a command register, an address register, and a queue register. The command register includes an n-bit first register column capable of storing n-bit data forming the command data. The address register includes an n-bit second register column capable of storing n-bit data forming the address data. The queue register includes a plurality of third register columns, each capable of storing at least (n+1) bit data, and each third register column is capable of storing the n-bit data forming the command data or the n-bit data forming the address data.

A semiconductor device includes a plurality of input/output (I/O) pads; a serial input pad; a serial output pad; a plurality of interface circuits respectively corresponding to the I/O pads; and a plurality of option setting circuits respectively corresponding to the interface circuits, suitable for setting options of the respective interface circuits, wherein the serial input pad, the interface circuits, the option setting circuits, and the serial output pad configure a serial chain.

Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.

An integrated circuit to drive a plurality of fluid actuation devices includes a configuration register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface and a data interface. The control logic enables writing to the configuration register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface.