A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.

A method described herein involves identifying a first time associated with a read operation that retrieves data of a write unit at a memory sub-system, identifying a second time associated with a write operation that stored the data of the write unit at the memory sub-system, and performing a refresh operation for the data of the write unit at the memory sub-system based on a difference between the first time associated with the read operation and the second time associated with the write operation.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

A clock circuit includes at least two first driving circuits and a plurality of discrete first wires located between adjacent first driving circuits, the adjacent first driving circuits are connected through at least one first wire and at least two second wires, the first driving circuits are connected with the second wires, all of the first wires connected between two second wires are connected in series with each other, the first wires are located on a first metal layer, the second wires are located on a second metal layer, and the second metal layer is above the first metal layer.