G11C7/1081

Pooled memory system enabled by monolithic in-package optical I/O

A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

Semiconductor devices having electro-optical substrates
11525956 · 2022-12-13 · ·

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide.

SYSTEMS HAVING DISAGGREGATED COMPONENTS COUPLED BY OPTICAL MEDIA
20220365583 · 2022-11-17 ·

A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical circuitry, and (3) an optical medium communicatively coupling the optical circuitry of the memory package with the additional optical circuitry of the processor package. Various other systems, apparatuses, and methods are also disclosed.

MEMORY DEVICES, COMPUTING DEVICES, AND METHODS FOR IN-MEMORY COMPUTING

A memory device includes a computing-in-memory macro and a clock generating circuit. The computing-in-memory macro is configured to perform in-memory computing based on a first clock signal. The clock generating circuit is arranged within the computing-in-memory macro and configured to generate the first clock signal. A frequency of the first clock signal is modified according to a condition of the computing-in-memory macro to cause the first clock signal to conform to an operation speed of the in-memory computing.

Scalable storage device

Implementations described and claimed herein provide a high-capacity, high-bandwidth scalable storage device. The scalable storage device includes a layer stack including at least one memory layer and at least one optical control layer positioned adjacent to the memory layer. The memory layer includes a plurality of memory cells and the optical control layer is adapted to receive optically-encoded read/write signals and to effect read and write operations to the plurality of memory cells through an electrical interface.

TIME DIVISION MULTIPLEXING (TDM) BASED OPTICAL TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)
20220059147 · 2022-02-24 ·

Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.

Semiconductor integrated circuit including at least one master chip and at least one slave chip
09773535 · 2017-09-26 · ·

A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
20170323674 · 2017-11-09 ·

Provided herein are a data input/output circuit and a semiconductor memory system having the same. The data input/output circuit may be coupled to an input/output line. The data input/output circuit may include a data input unit and a data output unit. The data input unit may deliver input data, inputted through the input/output line, to a page buffer during a data input period. The data output unit may deliver output data, outputted from the page buffer, to the input/output line during a data output period. The data input unit may include a signal reception unit coupled to the input/output line and configured to receive the input data from the input/output line; and a data delivery unit configured to deliver the input data inputted to the signal reception unit to the page buffer during the data input period.

Memory controller, memory system including the same, and electronic device including the memory system

A memory system in accordance with an embodiment of the inventive concept includes a memory controller comprising a controller optical transmission unit photoelectrically-converting a data signal to output a first optical modulation signal and a second optical modulation signal, a first memory device which is optically connected with the memory controller to receive the first optical modulation signal, and a second memory device which is optically connected with the memory controller to receive the second optical modulation signal. The first optical modulation signal and the second optical modulation signal are complementary to each other.

Time division multiplexing (TDM) based optical ternary content addressable memory (TCAM)

Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.