A neuromorphic hardware apparatus based on a resistive memory array includes a resistive memory array in which a plurality of synaptic resistor elements are arranged. Each synaptic resistor element is changed in its resistance value depending on a voltage pulse applied thereto and stores the resistance value for a predetermined time. The apparatus also includes a neuron circuit configured to receive an output signal from the resistive memory array and to output a voltage signal to another resistive memory array. The neuron circuit includes a temperature compensation unit, which compensates for an output voltage of the resistive memory array on the basis of an operating temperature of the resistive memory array. Even when a resistive memory array outputs an abnormal output depending on an operating temperature, by compensating a neuron circuit for an input value, it is possible to prevent an operation error from occurring.

A neuromorphic hardware apparatus based on a resistive memory array includes a resistive memory array in which a plurality of synaptic resistor elements are arranged. Each synaptic resistor element is changed in its resistance value depending on a voltage pulse applied thereto and stores the resistance value for a predetermined time. The apparatus also includes a neuron circuit configured to receive an output signal from the resistive memory array and to output a voltage signal to another resistive memory array. The neuron circuit includes a temperature compensation unit, which compensates for an output voltage of the resistive memory array on the basis of an operating temperature of the resistive memory array. Even when a resistive memory array outputs an abnormal output depending on an operating temperature, by compensating a neuron circuit for an input value, it is possible to prevent an operation error from occurring.

A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

A device includes a multiplication unit and a configurable summing unit. The multiplication unit is configured to receive data and weights for an Nth layer, where N is a positive integer. The multiplication unit is configured to multiply the data by the weights to provide multiplication results. The configurable summing unit is configured by Nth layer values to receive an Nth layer number of inputs and perform an Nth layer number of additions, and to sum the multiplication results and provide a configurable summing unit output.

A data processing system may include: a matrix splitting circuit configured to: split the matrix into a positive matrix and a negative matrix, and store the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory, respectively; a vector conversion circuit configured to generate an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element, and apply the offset vector to the row lines of the first sub array and the second sub array; and an offset correction circuit configured to generate an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix, and subtract the offset correction value from a computation value outputted from the first sub array and the second sub array,

A data processing system may include: a matrix splitting circuit configured to: split the matrix into a positive matrix and a negative matrix, and store the positive matrix and the negative matrix in a first sub array and a second sub array within the computation memory, respectively; a vector conversion circuit configured to generate an offset vector by adding, to elements within the vector, an offset for converting a negative element, which has a largest absolute value among the elements within the vector, into a zero element or a positive element, and apply the offset vector to the row lines of the first sub array and the second sub array; and an offset correction circuit configured to generate an offset correction value by subtracting a result of multiplying the offset and the negative matrix from a result of multiplying the offset and the positive matrix, and subtract the offset correction value from a computation value outputted from the first sub array and the second sub array,

A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.

A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.

In one embodiment, an electronic device includes a compute-in-memory (CIM) array that includes a plurality of columns. Each column includes a plurality of CIM cells connected to a corresponding read bitline, a plurality of offset cells configured to provide a programmable offset value for the column, and an analog-to-digital converter (ADC) having the corresponding bitline as a first input and configured to receive the programmable offset value. Each CIM cell is configured to store a corresponding weight.

In one embodiment, an electronic device includes a compute-in-memory (CIM) array that includes a plurality of columns. Each column includes a plurality of CIM cells connected to a corresponding read bitline, a plurality of offset cells configured to provide a programmable offset value for the column, and an analog-to-digital converter (ADC) having the corresponding bitline as a first input and configured to receive the programmable offset value. Each CIM cell is configured to store a corresponding weight.