A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

A dual-rail memory includes, in part, a memory array that operates using a first supply voltage, and a periphery circuit that operates using a second supply voltage. The periphery circuit includes, in part, a clock generation circuit and a comparator. The dual-rail memory also includes a level shifter that varies the voltage level of a number of signals of the memory between the first and second supply voltages. The clock generation circuit is adapted, among other operations, to generate a read clock signal in response to a read request signal. The level shifter is adapted to supply a reference wordline read signal in response to the read clock signal. The comparator is adapted to select a delay between the read clock signal and the reference wordline read signal in response to a difference between the first and second supply voltages.

A memory is presented. The memory includes a plurality of memory cells, a wordline coupled to the plurality of memory cells, a sense amplifier coupled to one of the plurality of memory cells, and a timing circuit configured to enable the sense amplifier. The timing circuit includes a delay stage and a dummy wordline. The dummy wordline is configured to emulate at least one portion of the wordline. An apparatus is presented. The apparatus include a first memory having a first wordline coupled to a first number of memory cells. A second memory having a second wordline coupled to a second number of memory cells. Each of the first memory and the second memory includes a timing circuit to enable a memory operation. The timing circuit includes a delay stage corresponding to loading of a third number of memory cells. The third number is different from the first number.

A microelectronic device comprises a microelectronic device structure comprising a section comprising page buffers, and an additional section horizontally neighboring the section and comprising page buffer drivers and a timing delay chain coupled to the page buffer drivers. Each of the page buffer drivers is coupled to different group of the page buffers than each other of the page buffer drivers. The timing delay chain comprises timing delay circuits coupled in series with one another. Each of the timing delay circuits is configured to adjustably delay propagation of a control signal therethrough. Memory devices, methods of operating memory devices, and electronic systems are also described.

Methods and devices for adjusting a read threshold voltage of bitlines are provided. One such method includes adjusting a read threshold voltage of bitlines coupled to memory points of a memory circuit. The read threshold voltage is initially set to a first value. First data are written in the memory points and second data are read from the memory points. The second data are compared to the first data, and the threshold voltage is decreased by a second value in response to a comparison error of one of the second data with the corresponding first data.

Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

A memory device includes a memory cell array and a transmitter, wherein the transmitter includes a pulse amplitude modulation (PAM) encoder configured to generate a PAM-n first input signal (where n is an integer greater than or equal to 4) from data read from the memory cell array; a pre-driver configured to generate a second input signal based on the first input signal and based on a calibration code signal, and output the second input signal using a first power voltage; and a driver configured to output a PAM-n DQ signal using a second power voltage lower than the first power voltage in response to the second input signal.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.