A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

Apparatuses and methods for temperature and process corner sensitive control of power gated domains are described. An example apparatus includes an internal circuit; a power supply line; and a power gating control circuit which responds, at least in part, to a first change from a first state to a second state of a control signal to initiate supplying a power supply voltage from the power supply line to the internal circuit, and continue supplying the power supply voltage from the power supply line to internal circuit for at least a timeout period from a second change from the second state to the first state of the control signal, in which the timeout period represent temperature dependency.

Apparatuses and methods related to logging failed authentication attempts. Failed authentication attempts can be logged in the circuitry by degrading the circuitry. The degradation can signal a fail authentication attempt while an amount of the degradation can represent a timing of the error.

Apparatuses and methods related to logging failed authentication attempts. Failed authentication attempts can be logged in the circuitry by degrading the circuitry. The degradation can signal a fail authentication attempt while an amount of the degradation can represent a timing of the error.

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided.

Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided.