In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

An amorphous dielectric includes a compound represented by A.sub.1+αBO.sub.xN.sub.y. −0.3≤α≤0.3, 0<x≤3.50, 0≤y≤1.00, and 6.70≤2x+3y≤7.30 are satisfied. A sum of an average valence of A-site ions and an average valence of B-site ions is 6.70 to 7.30.

A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.

A HfO2-based ferroelectric capacitor and a preparation method therefor, and a HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging the memory window of the ferroelectric memory is achieved by inserting an Al.sub.2O.sub.3 intercalation layer having a coefficient of thermal expansion smaller than TiN between a dielectric layer and an upper electrode (TiN) of the ferroelectric capacitor. The HfO.sub.2-based ferroelectric capacitor comprises a substrate layer, a lower electrode, a dielectric layer, an Al.sub.2O.sub.3 intercalation layer, an upper electrode and a metal protection layer from bottom to top. The memory window can be increased, information misreading is effectively prevented, and therefore, the reliability of the memory is improved.

An embodiment of the present disclosure provides a MIM capacitor by High-k dielectric and method for fabricating the same to prevent formation of oxygen-based interface films between a lower electrode and a dielectric layer, and between an upper electrode and a dielectric layer by stacking a first film formed of metal between the dielectric layer formed of a High-k material having a high dielectric constant and the lower electrode formed of metal, and a second film formed of metal between the dielectric layer and the upper electrode.

Provided is an electrolytic nickel foil including, on at least one surface thereof, a flat surface having the following surface roughness: a Ra of 0.05 μm or less, a Rz of 0.2 μm or less, and a Rt of 0.5 μm or less and a glossiness of 200 GU or more as determined by measuring a 60° specular reflection angle.

A capacitor component includes: a plurality of conductive nanowires disposed to be spaced apart from each other; first and second connecting conductive layers respectively disposed on one end and the other end of the plurality of conductive nanowires, and connected to the plurality of conductive nanowires; a conductive body surrounding the plurality of conductive nanowires; and a dielectric film disposed between the plurality of conductive nanowires, each of the first and second connecting conductive layers, and the conductive body.

The present invention includes a method of fabricating an integrated RF power condition capacitor with a capacitance greater than or equal to 1 nf and less than 1 mm.sup.2, and a device made by the method.

A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer from the portion of the second oxide layer. A semiconductor structure is also provided.

An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.