A plasma processing apparatus includes a stage provided in a processing container, and an upper electrode. The upper electrode includes a dielectric plate facing the stage, and a conductor formed on a surface of the dielectric plate opposite to a surface of the dielectric plate facing the stage. The dielectric plate includes a central portion, an outer peripheral portion, and an intermediate portion between the central portion and the outer peripheral portion. The intermediate portion has a thickness larger than the thicknesses of the central portion and the outer peripheral portion.

Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.

A controller includes an accumulation determiner configured to determine a first accumulation value that indicates an amount of accumulation of material on surfaces within a processing chamber and a pressure controller configured to obtain the first accumulation value, obtain at least one of a setpoint pressure an etching step and a duration of the etching step, and, to control the pressure within the processing chamber during the etching step, adjust a control parameter based on (i) the first accumulation value and (ii) the at least one of the setpoint pressure and the duration of the etching step.

A plasma processing apparatus is provided. The plasma processing apparatus is provided with an upper electrode, a lower electrode, and an electromagnetic wave emission port. The upper electrode is provided so as to allow discharging a processing gas into a processing container. The lower electrode is provided so as to holding a workpiece in the processing container. The electromagnetic wave emission port is provided at a height position between a height position of the upper electrode and a height position of the lower electrode, and is open toward a center of the processing container.

A method may include providing a set of features in a mask layer, wherein a given feature comprises a first dimension along a first direction, second dimension along a second direction, orthogonal to the first direction, and directing an angled ion beam to a first side region of the set of features in a first exposure, wherein the first side region is etched a first amount along the first direction. The method may include directing an angled deposition beam to a second side region of the set of features in a second exposure, wherein a protective layer is formed on the second side region, the second side region being oriented perpendicularly with respect to the first side region. The method may include directing the angled ion beam to the first side region in a third exposure, wherein the first side region is etched a second amount along the first direction.

Deposition methods and apparatus for conditioning a process kit to increase process kit lifetime are described. A nitride film formed on a process kit is exposed to conditioning process comprising nitrogen and hydrogen radicals to condition the nitride film to decrease particulate contamination from the process kit.

Embodiments disclosed herein include a monolithic source array. In an embodiment, the monolithic source array comprises a dielectric plate having a first surface and a second surface opposite from the first surface. The monolithic source array may further comprise a plurality of protrusions that extend out from the first surface of the dielectric plate, wherein the plurality of protrusions and the dielectric plate are a monolithic structure.

A semiconductor device manufacturing method comprising loading a substrate into a substrate treatment apparatus, performing a deposition process on the substrate, and cleaning the substrate treatment apparatus. The substrate treatment apparatus includes a housing defining a treatment area in which the deposition process is performed, a gas supply supplying a first process gas at a flow rate of 1000 sccm to 15000 sccm and supplying a second process gas, a remote plasma supply connected to the gas supply, generating a first process plasma and a second process plasma by applying RF power to plasma-process the first process gas and the second process gas, and a shower head installed in the housing to supply the first process plasma and the second process plasma to the treatment area. The second process plasma cleans a membrane material deposited on an inner wall of the housing.

A film forming method includes: preparing a substrate that includes a base substrate and a first conductive film that is formed on the base substrate; forming, on the first conductive film, a composite layer that includes layers of graphene and includes, as dopant atoms, a transition metal from 4th period to 6th period in a periodic table, excluding lanthanoids, between the layers of graphene; and forming, on the composite layer, a second conductive film which is electrically connected to the first conductive film via the composite layer.

An ultraviolet light-resistant article that includes: a substrate having a glass or glass-ceramic composition and first and second primary surfaces; an ultraviolet light-absorbing element having a an absorptivity greater than 50% at wavelengths from about 100 nm to about 380 nm and a thickness between about 10 nm and about 100 nm; and a dielectric stack formed with a plasma-enhanced process. Further, the light-absorbing element is between the substrate and the dielectric stack. Alternatively, the light-absorbing element can include one or more ultraviolet light-resistant layers disposed within the dielectric stack over the first primary surface.