A small-gap device system, preferably including two or more electrodes and one or more spacers maintaining a gap between two or more of the electrodes. A spacer for a small-gap device system, preferably including a plurality of legs defining a mesh structure. A method of spacer and/or small-gap device fabrication, preferably including: defining lateral features, depositing spacer material, selectively removing spacer material, separating the spacer from a fabrication substrate, and/or assembling the small-gap device.

A small-gap device system, preferably including two or more electrodes and one or more spacers maintaining a gap between two or more of the electrodes. A spacer for a small-gap device system, preferably including a plurality of legs defining a mesh structure. A method of spacer and/or small-gap device fabrication, preferably including: defining lateral features, depositing spacer material, selectively removing spacer material, separating the spacer from a fabrication substrate, and/or assembling the small-gap device.

A small-gap device system, preferably including two or more electrodes and one or more spacers maintaining a gap between two or more of the electrodes. A spacer for a small-gap device system, preferably including a plurality of legs defining a mesh structure. A method of spacer and/or small-gap device fabrication, preferably including: defining lateral features, depositing spacer material, selectively removing spacer material, separating the spacer from a fabrication substrate, and/or assembling the small-gap device.

The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end. The first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks. The second portion and the second end are outside the corresponding one of the plurality of dielectric blocks.

The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end. The first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks. The second portion and the second end are outside the corresponding one of the plurality of dielectric blocks.

The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end. The first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks. The second portion and the second end are outside the corresponding one of the plurality of dielectric blocks.

The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end. The first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks. The second portion and the second end are outside the corresponding one of the plurality of dielectric blocks.