A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

Laminate structures including hole plugs, and methods for forming a hole plug in a laminate structure are provided. A laminate structure may be formed with at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. A blind hole may be formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the blind hole including a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). Via fill ink may be disposed in the blind hole, and the via fill ink may be dried and/or cured to form a hole plug.

A method of and device for making a three dimensional electronic circuit. The method comprises coupling one or more magnet wires with a substrate along a surface contour of the substrate, immobilizing the one or more magnet wires on the substrate, and forming the electronic circuit by electrically coupling the one or more magnet wires with an integrated circuit chip.

A method for producing circuit board, including: adhering plastic deformable insulating material onto surface of laminate, which contains second-metal-layer of second metal, and first-metal-layer in pattern on second-metal-layer, and the surface of the laminate is surface of second-metal-layer where first-metal-layer is formed, and surface of first-metal-layer, followed by curing the material, and removing second-metal-layer to form plate structure to which first-metal-layer in pattern is formed; opening hole in cured material from surface of the plate structure opposite to surface thereof where first-metal-layer is formed, until the hole reaches first-metal-layer; filling the hole with electroconductive paste, to form the plate structure filled therewith; and laminating one plate structure filled therewith with the other plate structure filled therewith in manner that first-metal-layer of one plate structure filled therewith faces opening of the hole of other plate structure filled therewith, wherein first-metal-layer contains metal different from second metal.

A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.

A method for producing a printed circuit board structure comprising at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layer are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.

A method for electrical wiring of electronic components in switchgear construction, the method comprising the steps: a. providing a plurality of electronic components which are mounted on a shared workpiece, in particular on a mounting plate; b. wiring the electronic components according to a predetermined circuit diagram and in a predetermined order by at least one robot, wherein a cable sequence of pre-assembled cables is fed to the at least one robot and the cables are arranged in the predetermined order in the cable sequence; wherein the wiring comprises gripping a free cable end of the cable sequence by a multifunctional end effector of the robot, feeding the free cable end to an electrical connection of one of the electronic components by the multifunctional end effector, and detaching the cable from the cable sequence by a separation unit of the multifunctional end effector.

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

An electronic device and a method for manufacturing the same are disclosed. The method for manufacturing the electronic device includes the following steps: providing a substrate; forming a metal layer on the substrate, wherein the metal layer has a first surface; forming a first insulating layer on the first surface of the metal layer; forming a second insulating layer on the first insulating layer; etching the first insulating layer and the second insulating layer to form a contact hole, wherein the contact hole exposes a portion of the first surface; cleaning the portion of the first surface exposed by the contact hole with a solution; and forming a transparent conductive layer on the second insulating layer, wherein the transparent conductive layer electrically connects with the metal layer.