An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.

A vertical field effect transistor (VFET) cell implementing a VFET circuit over a plurality of gate grids includes: a 1.sup.st circuit including at least one VFET and provided over at least one gate grid; and a 2.sup.nd circuit including at least one VFET and provided over at least one gate grid formed on a left or right side of the 1.sup.st circuit, wherein a gate of the VFET of the 1.sup.st circuit is configured to share a gate signal or a source/drain signal of the VFET of the 2.sup.nd circuit, and the 1.sup.st circuit is an (X−1)-contacted poly pitch (CPP) circuit, which is (X−1) CPP wide, converted from an X-CPP circuit which is X CPP wide and performs a same logic function as the (X−1)-CPP circuit, X being an integer greater than 1.

An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

An integrated circuit is disclosure. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in the first layer parallel to the first pair of power rails, a first set of active areas. The integrated circuit further includes a first gate arranged along the second direction, between the first pair of power rails, and crossing the first set of active areas in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and a second gate and a third gate, in which the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor which is coupled to the control terminal of the third transistor.

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

A semiconductor structure includes a plurality of cells. Each cell has a plurality of transistors, a plurality of inner metal lines, two first backside power lines and one second backside power line. The inner metal lines, the first backside power lines and the second backside power line are disposed on a back side of the transistors. The inner metal lines, the first backside power lines and the second backside power line extend along a first axis. The second backside power line is disposed between the two first backside power lines. The inner metal lines are electrically connected to the first backside power lines and the transistors, and electrically connected to the second backside power line and the transistors. The cells are arranged along a second axis, the second axis being vertical to the first axis.

A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.