An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

In method for forming a semiconductor device, a first opening is formed in a dielectric stack that has a cylinder shape with a first sidewall. A first conductive layer is deposited along the first sidewall of the first opening and a first insulating layer is deposited along an inner sidewall of the first conductive layer. The dielectric stack is then etched along an inner sidewall of the first insulating layer so as to form a second opening that extends into the dielectric stack with a second sidewall. A second conductive layer is further formed along the second sidewall of the second opening and a second insulating layer is formed along an inner sidewall of the second conductive layer. A bottom of the second conductive layer is positioned below a bottom of the first conductive layer to form a staggered configuration.

A semiconductor device including a standard cell for implementing a logic element includes a first active region and a second active region extending in a second direction on a substrate and spaced apart from each other in a first direction perpendicular to the second direction, gate electrodes intersecting the first active region and the second active region, and source regions and drain regions formed on the first and second active regions at both sides of each of the gate electrodes. A boundary of the standard cell has a polygonal shape, excluding a quadrilateral shape, when viewed in a plan view. As a result, an area of the standard cell may be reduced to reduce a size of the semiconductor device.

A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.

A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.

A semiconductor device includes first and second active patterns respectively on the first and second active regions of a substrate, a gate electrode on the first and second channel patterns, active contacts electrically connected to at least one of the first and second source/drain patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the active and gate contacts and including a first and second power line, and first and second gate cutting patterns below the first and second power lines. The first active pattern may include first channel pattern between a pair of first source/drain patterns. The second active pattern may include a second channel pattern between a pair of second source/drain patterns. The first and second gate cutting patterns may cover the outermost side surfaces of the first and second channel patterns, respectively.

In method for forming a semiconductor device, a first opening is formed in a dielectric stack that has a cylinder shape with a first sidewall. A first conductive layer is deposited along the first sidewall of the first opening and a first insulating layer is deposited along an inner sidewall of the first conductive layer. The dielectric stack is then etched along an inner sidewall of the first insulating layer so as to form a second opening that extends into the dielectric stack with a second sidewall. A second conductive layer is further formed along the second sidewall of the second opening and a second insulating layer is formed along an inner sidewall of the second conductive layer. A bottom of the second conductive layer is positioned below a bottom of the first conductive layer to form a staggered configuration.