In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.

A cell on an IC includes a first set of M.sub.x layer interconnects coupled to a first voltage, a second set of M.sub.x layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the M.sub.x layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of M.sub.x layer interconnects is coupled to the CTM. The second set of M.sub.x layer interconnects is coupled to the CBM. The MIM capacitor structure is between the M.sub.x layer and an M.sub.x-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

A cell on an IC includes a first set of M.sub.x layer interconnects coupled to a first voltage, a second set of M.sub.x layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the M.sub.x layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of M.sub.x layer interconnects is coupled to the CTM. The second set of M.sub.x layer interconnects is coupled to the CBM. The MIM capacitor structure is between the M.sub.x layer and an M.sub.x-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

In some embodiments, the present disclosure relates to an integrated chip including a first transistor and a second transistor arranged over a substrate. The first transistor includes first and second source/drain regions over the substrate and includes a first channel structure directly between the first and second source/drain regions. A first gate electrode is arranged over the first channel structure and is between first and second air spacer structures. The second transistor includes third and fourth source/drain regions over the substrate and includes a second channel structure directly between the third and fourth source/drain regions. A second gate electrode is arranged over the second channel structure and is between third and fourth air spacer structures. The integrated chip further includes a high-k dielectric spacer structure over a low-k dielectric fin structure between the first and second channel structures to separate the first and second gate electrodes.

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.