A power electronics module and a method of producing a power electronics module. The power electronics module includes multiple of power electronic semiconductor chips incorporated in a housing and attached to a substrate, and a heat transfer structure attached to the substrate and having a bottom surface which forms an outer surface of the module and which is adapted to receive a surface of a cooling device, wherein the heat transfer structure includes a compressible base plate.

Disclosed is a light-emitting module, comprising: a circuit board, a conductive layer, a light-emitting device, and an adhesive material. The circuit board comprises a device-attachment area, the conductive layer being disposed on the device-attachment area, the light-emitting device being disposed on the conductive layer and electrically connected to the circuit board through the conductive layer, and the adhesive layer being used for connecting the light-emitting device to the circuit board, wherein a curing temperature of the adhesive layer is lower than a melting point of the conductive layer. Adopting the aforementioned technical means, the degree of offset in the position of the light-emitting device after reflow soldering can be greatly reduced. In addition, a vehicle lamp device using the light-emitting module is also provided.

Provided is a physical quantity measurement device in which a bonding temperature of a bonding layer is lowered to a temperature not affecting an operation of a semiconductor chip and an insulating property of the semiconductor chip and a base is secured. The physical quantity measurement device includes a base (diaphragm), a semiconductor chip (strain detection element) to measure a physical quantity on the basis of stress acting on the base, and a bonding layer to bond the semiconductor chip to the base. The bonding layer has a first bonding layer bonded to the semiconductor chip, a second bonding layer bonded to the base, and an insulating base material disposed between the first bonding layer and the second bonding layer. The first and second bonding layers and contain glass. A thermal expansion coefficient of the first bonding layer is equal to or lower than a thermal expansion coefficient of the second bonding layer, a softening point of the second bonding layer is equal to or lower than a heat resistant temperature of the semiconductor chip, and a softening point of the first bonding layer is equal to or lower than the softening point of the second bonding layer.

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

There is provided a method of performing a surface treatment with respect to a metal mounting table for mounting a substrate to be plasma-processed, the mounting table functioning as a lower electrode configured to generate a plasma by a high frequency power applied between an upper electrode and the lower electrode. The method includes: performing a first surface treatment by spraying a non-sublimation blast material as a non-sublimation material onto a mounting surface of the metal mounting table on which the substrate is mounted, followed by a second surface treatment by spraying a sublimation blast material as a sublimation material onto the mounting surface.

To provide a high-performance semiconductor sensor device and a method for manufacturing the semiconductor sensor device. This semiconductor sensor device has a sensor chip, and a first thin film formed on the sensor chip, said sensor chip being mechanically connected, via the first thin film, to a second thin film formed on a base formed of a polycrystalline material.

A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to 40 C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.

An apparatus may be provided. The apparatus may comprise a substrate and a circuit board. A ball grid array structure may be disposed between the substrate and the circuit board. In addition, a stand-off structure may be disposed between the substrate and the circuit board. The stand-off structure may be adjacent to the ball grid array structure.

An apparatus for bonding semiconductor chips may comprise transfer rails configured to transfer substrates, loading members configured to load the substrates onto the transfer rails, unloading members configured to unload the substrates from the transfer rails, a first wafer supply unit configured to supply a first wafer including semiconductor chips, and/or a bonding unit configured to bond the semiconductor chips to the substrates. An apparatus for bonding semiconductor chips may comprise a transfer rail configured to transfer substrates, loading members configured to load the substrates onto the transfer rail, unloading members configured to unload the substrates from the transfer rail, a buffer member at a side of the transfer rail configured to temporarily receive the substrates loaded by the loading members, a first wafer supply unit configured to supply a first wafer including semiconductor chips, and/or a bonding unit configured to bond the semiconductor chips to the substrates.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.