A semiconductor package includes a semiconductor die and an encapsulant layer. A mark is formed on a surface of the encapsulant layer. A damage barrier layer is disposed between the mark and the semiconductor die. The damage barrier layer blocks the propagation of laser light used to form the mark from reaching the semiconductor die.

An acoustic wave device includes an acoustic wave substrate including a first main surface and a second main surface, IDT electrodes provided on the first main surface, and sealing resin covering at least the second main surface of the acoustic wave substrate. A hollow is provided in a region where the IDT electrodes on the first main surface of the acoustic wave substrate is located. The sealing resin has through-holes each extending from a top surface 13B of the sealing resin to the second main surface of the acoustic wave substrate. The acoustic wave substrate is made of silicon or includes a layer made of silicon.

A ceramic circuit board includes a ceramic base material, a metal layer (first metal layer), and a marker portion. The marker portion is formed on the surface of the first metal layer. The surface of the metal layer (first metal layer) may be plated. When the surface of the metal layer (first metal layer) is plated, the marker portion may be formed on the plating.

A multijunction solar cell including an upper first solar subcell having a first band gap and positioned for receiving an incoming light beam; a second solar subcell disposed below and adjacent to and lattice matched with said upper first solar subcell, and having a second band gap smaller than said first band gap; wherein the upper first solar subcell covers less than the entire upper surface of the second solar subcell, leaving an exposed portion of the second solar subcell that lies in the path of the incoming light beam.

A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern formed using laser marking on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the at least one code pattern is visible from a backside of the chip, the at least one code pattern represents a binary number having four bits; and the binary number represents a decimal number to represent a tracing number of the chip.

A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

Hydrophobic, tough, photoimageable, functionalized polyimide formulations have been discovered that can be UV cured and developed in cyclopentanone. The present invention formulations can be used as passivation and redistribution layers with patterning provided by photolithograph, for the redistribution of I/O pads on fan-out RDL applications. The curable polyimide formulations reduce stress on thin wafers, when compared to conventional polyimide formulations, and provide low modulus, hydrophobic solder mask. These materials can serve as protective layers in any applications in which a thin, flexible, and hydrophobic polymer is required, that also has high tensile strength and high elongation at break.