A light-receiving device includes: a first chip having a pixel region in which a sensor pixel is provided; a second chip including a processing circuit that performs signal processing on a sensor signal outputted from the sensor pixel, the second chip being stacked on the first chip; and a first alignment mark provided in the pixel region of the first chip to correspond to a second alignment mark provided in the second chip.

A method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region; forming a plurality of trenches in the first region of the substrate; forming a multi-layer stack over the substrate and in the trenches; and patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, where the multi-layer stack includes at least one of first semiconductor layers and at least one of second semiconductor layer stacked alternately, and the plurality of trenches are in corresponding ones of the first fins.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

A process of overlay offset measurement includes providing a substrate; forming a first pattern layer with a predetermined first pattern on the substrate; forming a first photoresist layer on the substrate and the first pattern layer; forming a second photoresist layer on the first photoresist layer; forming a second pattern layer with a predetermined second pattern on the second photoresist layer; patterning the second photoresist layer to form a trench having a predetermined third pattern being substantially aligned with the predetermined first pattern of the first pattern layer; and performing overlay offset measurement according to the second pattern layer and the trench.

A display device includes a substrate having a first surface and a second surface opposite to the first surface. The display device includes a first conductive layer disposed on the first surface and a second conductive layer disposed on the second surface. The first conductive layer and the second conductive layer are disposed on the opposite sides of the substrate. The display device includes a connective portion at least partially disposed in the substrate and penetrating from the first surface to the second surface. The first conductive layer is electrically connected to the second conductive layer through the connective portion. The display device includes a light-emitting element disposed on the first surface and an insulation layer disposed on the first conductive layer. Along a direction perpendicular to the first surface, the first electrode and the second electrode of the light-emitting element are not overlapped with the connective portion.

A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.