A wafer producing method includes a peel-off layer forming step of forming a peel-off layer by positioning a focused spot of a laser beam having a wavelength transmittable through an ingot to a depth corresponding to a thickness of the wafer to be produced from the ingot from a first end surface of the ingot and applying the laser beam to the ingot, a first chamfered portion forming step of forming a first chamfered portion by applying, from the first end surface side to a peripheral surplus region of the wafer, a laser beam having a wavelength absorbable by the wafer, a peeling-off step of peeling off the wafer to be produced, and a second chamfered portion forming step of forming a second chamfered portion by applying, from a peel-off surface side of the wafer, the laser beam having a wavelength absorbable by the wafer.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

A semiconductor device capable of improving the quality of a pixel region, an electronic apparatus including the semiconductor device, and a method for manufacturing the semiconductor device are to be provided. The present technology provides a semiconductor device that includes: a first substrate in which a pixel region including a pixel having a photoelectric conversion unit is formed; and a second substrate in which a logic circuit that processes a signal output from the pixel region is formed, the first substrate and the second substrate being stacked. In the semiconductor device, at least one of marks including a mark to be used in an exposure process during the manufacture of the semiconductor device and/or a mark to be used in an inspection process for the semiconductor device is formed in a first region that is a region between a first scribe region that is a peripheral portion of the first substrate and the pixel region and/or in a second region that is a region between a second scribe region that is a peripheral portion of the second substrate and a region corresponding to the pixel region in the second substrate.

Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.