A semiconductor package includes a semiconductor die and an encapsulant layer. A mark is formed on a surface of the encapsulant layer. A damage barrier layer is disposed between the mark and the semiconductor die. The damage barrier layer blocks the propagation of laser light used to form the mark from reaching the semiconductor die.

An acoustic wave device includes an acoustic wave substrate including a first main surface and a second main surface, IDT electrodes provided on the first main surface, and sealing resin covering at least the second main surface of the acoustic wave substrate. A hollow is provided in a region where the IDT electrodes on the first main surface of the acoustic wave substrate is located. The sealing resin has through-holes each extending from a top surface 13B of the sealing resin to the second main surface of the acoustic wave substrate. The acoustic wave substrate is made of silicon or includes a layer made of silicon.

A ceramic circuit board includes a ceramic base material, a metal layer (first metal layer), and a marker portion. The marker portion is formed on the surface of the first metal layer. The surface of the metal layer (first metal layer) may be plated. When the surface of the metal layer (first metal layer) is plated, the marker portion may be formed on the plating.

The present disclosure relates to an integrated package having an active area, an electrical routing circuit, an optical routing circuit, and a vacuum vessel. Methods of making such a package are also described herein.

A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.

The present invention relates to an improved electronic circuit, as well as an improved substrate with electronic circuits, with an identification pattern. The invention makes it possible to make them identifiable and amongst other things to retrace the circuit(s) in this way through the production process. Furthermore, the invention relates to an improved production method for circuits and substrates according to the invention.

Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.

A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern formed using laser marking on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the at least one code pattern is visible from a backside of the chip, the at least one code pattern represents a binary number having four bits; and the binary number represents a decimal number to represent a tracing number of the chip.

A method for manufacturing a multilayer wiring substrate includes forming a resist layer having mask pattern, forming a conductor layer having conductor pattern using the resist layer, removing the resist layer, forming an insulating layer on the conductor layer such that the insulating layer is laminated on the conductor layer, forming a subsequent resist layer having mask pattern such that the subsequent resist layer is formed on the insulating layer, and forming a subsequent conductor layer having conductor pattern using the subsequent resist layer. The forming of the resist layer includes conducting first correction in which formation position of entire mask pattern of the resist layer is corrected with respect to reference position, and conducting second correction in which shape of the mask pattern of the resist layer is corrected with respect to reference shape, and the forming of the subsequent resist layer does not include conducting the second correction.

A method of forming a self-aligned waveguide is provided. The method includes forming a first alignment feature on a packaged semiconductor device and a second alignment feature on a waveguide structure. A solder material is applied to the first alignment feature or the second alignment feature. The waveguide structure is placed onto the packaged semiconductor device such that the second alignment feature overlaps the first alignment feature. The solder material is reflowed to cause the waveguide structure to align with the packaged semiconductor device.