Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

A semiconductor device comprises a lead, a board, and an electrically conductive layer on the board. The lead comprises a longitudinal axis and is soldered to the electrically conductive layer. The semiconductor device further comprises a first solder dam edge and a second solder dam edge, each positioned on the lead not more than 10 mils apart from each other along the longitudinal axis.

A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

In an embodiment of the present disclosure, a wiring base includes an insulative base, a signal conductor, a first lead terminal, a first ground conductor, and a second lead terminal. The insulative base includes a first face and a second face. The signal conductor is provided on the first face. The first lead terminal is provided on the signal conductor. The first lead terminal extends in a first direction and includes a portion projecting from the insulative base in plan view toward the first face. The first ground conductor is provided on the second face. The second lead terminal is provided on the first ground conductor. At least a part of the second lead terminal overlaps the first lead terminal in the plan view toward the first face.

A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

A semiconductor device includes: a first semiconductor chip including a first coil that generates a magnetic field signal; a wiring board including a second coil, a third coil, and a twisted pair wiring, the second coil being disposed to face the first coil and receiving the magnetic field signal generated by the first coil, the twisted pair wiring connecting the second coil with the third coil; and a second semiconductor chip including a fourth coil disposed to face the third coil and receiving a magnetic field signal generated by the third coil.

The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

A method of forming a self-aligned waveguide is provided. The method includes providing a radio frequency (RF) interposer. The RF interposer includes a non-conductive substrate, a radiating element formed on the non-conductive substrate, and a cavity formed in the non-conductive substrate. A packaged semiconductor die is affixed in the cavity of the RF interposer. A conductive material is dispensed to form a conductive path between a conductive connector of the packaged semiconductor die and the radiating element.