A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part.

An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 μm. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A semiconductor device includes a wiring substrate including a first wiring layer. The first wiring layer includes a first wiring pattern which is a transmission path of a first signal, a second wiring pattern which is a transmission path of a second signal and which is arranged next to one side of the first wiring pattern, and a third wiring pattern which is a transmission path of a third signal and which is arranged next to the other side of the first wiring pattern. A wiring pattern group including the first through third wiring patterns has: a first portion in which wiring widths of the first through third wiring patterns are equal to each other; and a second portion in which the wiring width of the first wiring pattern is larger than the wiring width of each of the second and third wiring patterns.

A low-voltage varistor includes a cured body of a resin composition for forming the low-voltage varistor. The resin composition includes: (A) at least one selected from carbon nanotubes and carbon aerogels; and (B) at least one selected from epoxy resin and acrylic resin.

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.

A substrate has an upper main surface and a lower main surface arranged in an up-down direction. The metal member is provided on the upper main surface of the substrate. The metal member includes a plate-shaped portion and one or more foot portions. The plate-shaped portion has a front main surface and a back main surface arranged in a front-back direction when viewed in the up-down direction. The one or more foot portions extend backward from the lower side by bending the metal member at the lower side of the plate-shaped portion. A line extending in a predetermined direction is provided on the front main surface, the back main surface, the outer surface of the portion where the metal member is bent, and the inner surface of the portion where the metal member is bent.

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

A semiconductor device includes a substrate and a first conductive layer formed over a first surface of the substrate. The first conductive layer is patterned into a first portion of a first passive circuit element. The first conductive layer is patterned to include a first coiled portion. A second conductive layer is formed over a second surface of the substrate. The second conductive layer is patterned into a second portion of the first passive circuit element. The second conductive layer is patterned to include a second coiled portion exhibiting mutual inductance with the first coiled portion. A conductive via formed through the substrate is coupled between the first conductive layer and second conductive layer. A semiconductor component is disposed over the substrate and electrically coupled to the first passive circuit element. An encapsulant is deposited over the semiconductor component and substrate. The substrate is mounted to a printed circuit board.