A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A 2nd signal line has impedance lower than impedance of a 1st signal line. A capacitor includes a 1st extension part and a 2nd extension part, a 1st ground part and a 2nd ground part. The 1st extension part and the 2nd extension part are connected to a 2nd signal line and are provided on an insulation substrate to extend along a longitudinal direction of the 2nd signal line. The 1st ground part and the 2nd ground part are at least a part of a ground pattern, and are provided between the 1st extension part and the 2nd extension part and the 2nd signal line, and between the 1st extension part and the 2nd extension part and an end part of the insulation substrate, to be electrically coupled with the 1st extension part and the 2nd extension part.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

A semiconductor device comprises; a lead frame having leads and a die pad; a printed circuit board including an electrode for the connection of each of the leads and the die pad, a wiring pattern, and an opening exposing a part of a surface of the die pad; the semiconductor element for processing a high frequency signal, mounted on a surface of a metal block bonded to the surface of the die pad exposed through the opening, and connected to the wiring pattern with a metal wire; electronic components connected to the wiring pattern and mounted on a surface of the printed circuit board; and a sealing resin to seal the printed circuit board, the semiconductor element, the electronic components, and the metal wire so as to expose rear surfaces of the leads and the die pad.

Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A semiconductor device according to one embodiment includes: a semiconductor chip having a transistor and a drain pad provided on a board; a capacitor having an upper electrode and a lower electrode interposing a dielectric; a pad; and an empty pad provided on the board of the semiconductor chip. The semiconductor device further includes: a first wire connecting the pad and the drain pad of the semiconductor chip to each other; a second wire connecting the empty pad and the upper electrode of the capacitor to each other; and a third wire connecting the pad and the empty pad to each other.