Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.

An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.

Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bump structure overlying a bond pad. The bond pad is disposed over a semiconductor substrate. An etch stop layer overlies the bond pad. A buffer layer is disposed over the bond pad and separates the etch stop layer and the bond pad. The bump structure includes a base portion contacting an upper surface of the bond pad and an upper portion extending through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter being greater than the second width or diameter.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

The present application discloses a semiconductor device with two stress-relieving structures and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a first stress-relieving structure including a first conductive frame positioned above the semiconductor substrate and a plurality of first insulating pillars positioned within the conductive frame, a second stress-relieving structure including a plurality of second conductive pillars positioned above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars is positioned within the second insulating frame, and a conductive structure including a supporting portion positioned above the second stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. The plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

A bump pad enclosure providing an improved reliability of a bump connection is provided. The bump pad enclosure comprises an electrode pad, a UBM and a first shield. The first shield covers at least a first perimeter area of the electrode pad. The first shield is provided and configured to shield the first perimeter area from a detrimental influence of the environment.

The present application discloses a semiconductor device with two stress-relieving structures and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a first stress-relieving structure including a first conductive frame positioned above the semiconductor substrate and a plurality of first insulating pillars positioned within the conductive frame, a second stress-relieving structure including a plurality of second conductive pillars positioned above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars is positioned within the second insulating frame, and a conductive structure including a supporting portion positioned above the second stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. The plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame.