A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

Disclosed is a semiconductor package comprising a substrate that includes a plurality of substrate pads on a top surface of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, and a plurality of first bonding wires on a top surface of the first semiconductor chip and coupled to the substrate pads. The first semiconductor chip includes a first lower signal pad, a second lower signal pad laterally spaced apart from the first lower signal pad, and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad. One of the first bonding wires is coupled to the first lower signal pad. Any of the first bonding wires is not on a top surface of the second lower signal pad.

A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a first electrode comprising a first portion, a second portion, and a sheet portion connecting the first portion to the second portion. A ferroelectric material is over the sheet portion. A second electrode is over the ferroelectric material.

A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.

A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.

A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

A bonded structure is disclosed. The bonded structure can include a first element that includes a first bonding layer, the first bonding layer that has a first contact pad and a routing trace. The routing trace is formed at the same level as the first contact pad. The bonded structure can include a second element that includes a second bonding layer that has a second contact pad. The first element and the second element are directly bonded such that the first contact pad and the second contact pad are directly bonded without an intervening adhesive